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CY7C460A/CY7C462A CY7C464A/CY7C466A
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
Features
* High-speed, low-power, first-in first-out (FIFO) memories * 8K x 9 FIFO (CY7C460A) * 16K x 9 FIFO (CY7C462A) * 32K x 9 FIFO (CY7C464A) * 64K x 9 FIFO (CY7C466A) * 10-ns access times, 20-ns read/write cycle times * High-speed 50-MHz read/write independent of depth/width * Low operating power -- ICC= 60 mA * * * * * * * * * * * -- ISB =8 mA Asynchronous read/write Empty and Full flags Half Full flag (in standalone mode) Retransmit (in standalone mode) TTL-compatible Width and Depth Expansion Capability 5V 10% supply PLCC, LCC, 300-mil and 600-mil DIP packaging Three-state outputs Pin compatible density upgrade to CY7C42X/46X family Pin compatible and functionally equivalent to IDT7205, IDT7206, IDT7207, IDT7208
Functional Description
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in first-out (FIFO) memories. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another by passing tokens. The read and write operations may be asynchronous; each can occur at a rate of up to 50 MHz. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH. A Half Full (HF) output flag is provided that is valid in the standalone (single device) and width expansion configurations. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated. In the standalone and width expansion configurations, a LOW on the Retransmit (RT) input causes the FIFOs to retransmit the data. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data. The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are fabricated using Cypress's advanced 0.5 RAM3 CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and the use of guard rings.
Logic Block Diagram
DATAINPUTS (D0 -D 8 )
Pin Configurations
PLCC/LCC Top View
V cc D 4 D 5 NC D 3 D 8 W
DIP Top View W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 7C460A 23 7C462A 7C464A 22 7C466A 21 20 19 18 17 16 15
W
WRITE CONTROL WRITE POINTER DUAL PORT RAM ARRAY 8K x 9 16K x 9 32K x 9 64K x 9 READ POINTER
D2 D1 D0 XI FF Q0 Q1 THREE- STATE BUFFERS DATAOUTPUTS (Q0 -Q 8 ) NC Q2
4 5 6 7 8 9 10 11 12
3
2
1
32 31 30 29 28 27
D6 D7 NC FL/RT MR EF XO/HF Q7 Q6
7C460A 7C462A 7C464A 7C466A
26 25 24 23 22
13 21 14 15 16 17 18 19 20 Q 3 Q 8 GND NC R Q 4 Q 5
R
READ CONTROL
RESET LOGIC
MR FL/RT
C46XA-2
VCC D4 D5 D6 D7 FL/RT MR EF XO/HF Q7 Q6 Q5 Q4 R
C46XA-3
FLAG LOGIC EXPANSION LOGIC
EF FF
XI
XO/HF
C46XA-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 October 4, 1999
CY7C460A/CY7C462A CY7C464A/CY7C466A
Selection Guide
7C460A-10 7C462A-10 7C464A-10 7C466A-10 Frequency (MHz) Maximum Access Time (ns) 50 10 7C460A-15 7C462A-15 7C464A-15 7C466A-15 40 15 7C460A-25 7C462A-25 7C464A-25 7C466A-25 28.5 25
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to +150C Ambient Temperature with Power Applied .............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Power Dissipation .......................................................... 1.0W
Output Current, into Outputs (LOW)............................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Military[1] Ambient Temperature 0C to + 70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[2]
7C460A/462A/464A/466A (-10,-15,-25) Parameter VOH VOL VIH VIL IIX IOZ ICC ISB Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current GND < VI < VCC R > VIH, GND < VO < V CC VCC = Max., IOUT = 0 mA, Freq. = 20 MHz All Inputs = VIH min. Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -10 -10 Min. 2.4 0.4 VCC 0.8 +10 +10 60 8 Max. Unit V V V V A A mA mA
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 4.5V Max. 10 12 Unit pF pF
Notes: 1. TA is the "instant on" case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second. 4. Tested initially and after any design or process changes that may affect these parameters.
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CY7C460A/CY7C462A CY7C464A/CY7C466A
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 333
C460A-4
R1 500
5V OUTPUT 5 pF INCLUDING JIG AND SCOPE
R1 500 3.0V R2 333
C460A-5
ALL INPUT PULSES 90% 10% 90% 10% 5 ns
C460A-6
GND 5 ns
(a)
(b)
THEVENIN EQUIVALENT 200 OUTPUT 2V
Switching Characteristics Over the Operating Range[2, 5]
7C460A-10 7C462A-10 7C464A-10 7C466A-10 Parameter tRC tA tRR tPR tLZR tDVR[6] tHZR[6] tWC tPW tHWZ tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR tEFL tHFH tFFH tREF tRFF Description Read Cycle Time Access Time Read Recovery Time Read Pulse Width Read LOW to Low Z Data Valid After Read HIGH Read HIGH to High Z Write Cycle Time Write Pulse Width Write HIGH to Low Z Write Recovery Time Data Set-Up Time Data Hold Time MR Cycle Time MR Pulse Width MR Recovery Time Read HIGH to MR HIGH Write HIGH to MR HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Recovery Time MR to EF LOW MR to HF HIGH MR to FF HIGH Read LOW to EF LOW Read HIGH to FF HIGH 20 10 5 10 9 0 20 10 10 10 10 20 10 10 20 20 20 10 10 10 10 3 3 15 25 15 5 10 9 0 25 15 10 15 15 25 15 10 25 25 25 15 15 Min. 20 10 10 15 3 3 15 35 25 5 10 9 0 35 25 10 25 25 35 25 10 35 35 35 25 25 Max. 7C460A-15 7C462A-15 7C464A-15 7C466A-15 Min. 25 15 10 25 3 3 18 Max. 7C460A-25 7C462A-25 7C464A-25 7C466A-25 Min. 35 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load capacitance, as in part (a) of AC Test Loads, unless otherwise specified. 6. t HZR and tDVR use capacitance loading as in part (b) of AC Test Loads.
3
CY7C460A/CY7C462A CY7C464A/CY7C466A
Switching Characteristics Over the Operating Range[2, 5] (continued)
7C460A-10 7C462A-10 7C464A-10 7C466A-10 Parameter tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH Description Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF LOW Read HIGH to HF HIGH Effective Read from Write HIGH Effective Read Pulse Width After EF HIGH Effective Write from Read HIGH Effective Write Pulse Width After FF HIGH Expansion Out LOW Delay from Clock Expansion Out HIGH Delay from Clock 10 10 10 10 10 15 15 15 Min. Max. 10 10 10 10 10 15 15 25 25 25 7C460A-15 7C462A-15 7C464A-15 7C466A-15 Min. Max. 15 15 15 15 15 25 25 7C460A-25 7C462A-25 7C464A-25 7C466A-25 Min. Max. 25 25 35 35 25 Unit ns ns ns ns ns ns ns ns ns ns
4
CY7C460A/CY7C462A CY7C464A/CY7C466A
Switching Waveforms[7]
Asynchronous Read and Write
tRC tA R tLZR Q0-Q 8 tPW W tSD D0-D 8 tHD tSD tHD
C460A-7
tPR tRR tA
tDVR DATA VALID tWC tWR
tHZR DATA VALID tPW
DATA VALID
DATA VALID
Master Reset
MR R, W
[8]
tMRSC [9] tPMR
EF
tEFL tHFH
tRPW tWPW tRMR
HF tFFH FF
C460A-8
Half Full Flag
HALF FULL W tRHF R tWHF HF
C460A-9
HALF FULL+1
HALF FULL
Notes: 7. A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe transition causes a LOW-to-HIGH flag transition. 8. W and R = VIH around the rising edge of MR. 9. tMSRC = t PMR + t RMR
5
CY7C460A/CY7C462A CY7C464A/CY7C466A
Switching Waveforms[7] (continued)
Last Write to First Read Full Flag
LAST WRITE R FIRST READ ADDITIONAL READS FIRST WRITE
W tWFF FF
C460A-10
tRFF
Last READ to First WRITE Empty Flag
LAST READ W FIRST WRITE ADDITIONAL WRITES FIRST READ
R tREF EF tA VALID VALID
C460A-11
tWEF
DATA OUT
Retransmit
[10,11]
tRTC tPRT FL/RT
R,W tRTR tRTC tRTR
C460A-12
Notes: 10. tRTC = tPRT + tRTR. 11. EF, HF, and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t RTC, except for the CY7C46x-20 (Military), whose flags will be valid after tRTC + 10 ns.
6
CY7C460A/CY7C462A CY7C464A/CY7C466A
Switching Waveforms[7] (continued)
Full Flag and Write Data Flow-Through Mode
R tWAF W tRFF tWFF tWPF
FF tHD DATA IN tA DATA OUT DATA VALID
C460A-13
DATA VALID tSD
Empty Flag and Read Data Flow-Through Mode
DATA IN W tRAE R tREF EF tRPE
tWEF tHWZ
tA DATA VALID
C460A-14
DATA OUT
7
CY7C460A/CY7C462A CY7C464A/CY7C466A
Switching Waveforms[7] (continued)
Expansion TimingDiagrams
W tWR t XOL XO1(XI2)
[12]
t XOH
tSD D0-D 8
tHD
tSD
tHD
DATA VALID
DATA VALID
C460A-15
R tRR tXOL t XOH
XO1(XI2)
[12]
tHZR tLZR Q0 -Q8 tA
Note: 12. Expansion out of device 1 (XO1) is connected to expansion in of device 2 (XI2).
tDVR DATA VALID tA
tDVR DATA VALID
C460A-16
Architecture
Resetting the FIFO Upon power-up, the FIFO must be reset with a master reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF), and Full flags (FF) being HIGH. Read (R) and Write (W) must be HIGH tRPW/tWPW before and tRMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. Writing Data to the FIFO The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D0-D8) tSD before and tHD after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs tWEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW tWHF after the falling edge of W following the FIFO actually being half full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tRHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF
is available in standalone and width expansion modes. FF goes LOW tWFF after the falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO. Reading Data from the FIFO The falling edge of R initiates a read cycle if the EF is not LOW. Data outputs (Q 0-Q8) are in a high-impedance condition between read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. When the FIFO is empty, the outputs are in a high-impedance state. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read tWEF after a valid write. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a num-
8
CY7C460A/CY7C462A CY7C464A/CY7C466A
ber of writes equal-to-or-less-than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and tRTR after retransmit is LOW. With every read cycle after retransmit, previously accessed data is read and the read pointer incremented until equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Standalone/Width Expansion Modes Standalone and width expansion modes are set by grounding expansion in (XI) and tying first load (FL) to VCC prior to a MR cycle. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. Depth Expansion Mode (see Figure 1) Depth expansion mode is entered when, during a MR cycle, expansion out (XO) of one device is connected to expansion in (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode, the first load (FL) input, when grounded, indicates that this is the first part to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and is pulsed LOW again when the last physical location is read. Only one FIFO is enabled for Read and one is enabled for Write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created with word widths in increments of nine. When expanding in depth, a composite FF is created by ORing the FFs together. Likewise, a composite EF is created by ORing EFs together. HF and RT functions are not available in depth expansion mode.
XO W FF D0-8 9 9 CY7C460A CY7C462A CY7C464A CY7C466A FL EF 9 Q0-8 R
VCC
XI
XO
FULL 9
FF CY7C460A CY7C462A CY7C464A CY7C466A
EF
EMPTY
FL
XI
XO
FF 9 CY7C460A CY7C462A CY7C464A CY7C466A
*
EF
RS
FL
XI
* FIRST DEVICE C460A-17
Figure 1. Depth Expansion
9
CY7C460A/CY7C462A CY7C464A/CY7C466A
Ordering Information
8K x 9 Asynchronous FIFO Speed (ns) 10 Ordering Code CY7C460A-10JC CY7C460A-10PC CY7C460A-10PTC CY7C460A-10JI 15 CY7C460A-15JC CY7C460A-15PC CY7C460A-15PTC 25 CY7C460A-25JC CY7C460A-25PC CY7C460A-25PTC Package Name J65 P15 P21 J65 J65 P15 P21 J65 P15 P21 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP Commercial Industrial Commercial Operating Range Commercial
16K x 9 Asynchronous FIFO Speed (ns) 10 Ordering Code CY7C462A-10JC CY7C462A-10PC CY7C462A-10PTC CY7C462A-10JI 15 CY7C462A-15JC CY7C462A-15PC CY7C462A-15PTC 25 CY7C462A-25JC CY7C462A-25PC CY7C462A-25PTC Package Name J65 P15 P21 J65 J65 P15 P21 J65 P15 P21 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP Commercial Industrial Commercial Operating Range Commercial
32K x 9 Asynchronous FIFO Speed (ns) 10 Ordering Code CY7C464A-10JC CY7C464A-10PC CY7C464A-10PTC CY7C464A-10JI 15 CY7C464A-15JC CY7C464A-15PC CY7C464A-15PTC CY7C464A-15LMB 25 CY7C464A-25JC CY7C464A-25PC CY7C464A-25PTC Package Name J65 P15 P21 J65 J65 P15 P21 L55 J65 P15 P21 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP Military Commercial Industrial Commercial Operating Range Commercial
10
CY7C460A/CY7C462A CY7C464A/CY7C466A
Ordering Information (continued)
64K x 9 Asynchronous FIFO Speed (ns) 10 Ordering Code CY7C466A-10JC CY7C466A-10PC CY7C466A-10PTC CY7C466A-10JI 15 CY7C466A-15JC CY7C466A-15PC CY7C466A-15PTC CY7C466A-15LMB 25 CY7C466A-25JC CY7C466A-25PC CY7C466A-25PTC Package Name J65 P15 P21 J65 J65 P15 P21 L55 J65 P15 P21 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 28-Lead (300-Mil) Molded DIP Military Commercial Industrial Commercial Operating Range Commercial
11
CY7C460A/CY7C462A CY7C464A/CY7C466A
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL Max. IIX ICC ISB1 ISB2 IOS IOZ Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tRC tA tRR tPR tLZR tDVR tHZR tWC tPW tHWZ tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR tEFL tHFH tFFH tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH
Switching Characteristics
Parameter Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
Document #: 38-00627-A
12
CY7C460A/CY7C462A CY7C464A/CY7C466A
Package Diagrams
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068
13
CY7C460A/CY7C462A CY7C464A/CY7C466A
Package Diagrams (continued)
28-Lead (600-Mil) Molded DIP P15
51-85017-A
28-Lead (300-Mil) Molded DIP P21
51-85014-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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